School of Computer Science

Computer Structure

0368-2159

Semester א, תשס"ו 2005-6 (Winter)

Lecturers:	Yehuda Afek	<afek at tau.ac.il>
	Natan Intrator	<nin at post.tau.ac.il>
Teaching Assistant	Ori Shalev	<orish at post.tau.ac.il>

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Administration & Messages

· TARGILIM (homeworks) Home work(s) grade calculation: To get the full grade on the home works you have to submit **ALL** the exercises. The home works grade will be the average of all of them.

· Lectures:

Tuesday	10:00-13:00	Orenstein 111
Wednesday	10:00-13:00	Orenstein 103

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Intel 2004 announcement

Suggested Books

· For the first part of the course:  V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982

· For the second part of the course:  Patterson Hennessy  Computer Organization Design, The Hardware/Software Interface. Morgan Kaufmann, 1998     Slides

· Older course book for the first part of the course:  H. Taub Digital Circuits and Microprocessors. McGraw-Hill, 1982

Course outline

· Introduction

An introduction to the course,

What is it Computer Structure?

The importance of Instruction sets

Memory hierarchies
Technological forces driving computer structure
Silicon -> Transistors -> logical gates
Implementing basic logical circuits from CMOS transistors

. Representation of numbers

Binary, Octal and Hexadecimal number systems

Bases transfer of integers and fractions

The one's complement and two's complement

Representation of signed numbers

· Algebra of logical variables

Logical variables and functions
The OR, AND, NOT functions
Boolean Algebra Theorems
De'Morgan's Theorem
The XOR, NAND and NOR functions
Universal System

· Karnaugh Maps, Combinatorial Circuits

Simplification of Logical functions using Boolean Algebra Theorems
Simplification using Karnaugh Maps
Circuit implementation
The Don't care utility for function minimization

· Basic Logic Building Blocks (Mux, Decoder)

Decoders and Encoders (mux)

· Flip Flops

A latch with NAND gates
The need for latch and synchronization
Clocked FF
Truth table and timing diagram for a FF
Two phase clocking and the Master/Slave RS FF
The JK FF, D and T flip-flops
Shift registers

· Registers, Counters, Simplification of Logical Functions

Serial to parallel
Parallel to serial
Serial implementation of a full adder
Counters and dividers
Ripple counter and a synchronous counter
Non-binary counters

· Sequential Circuits

The state and transition diagrams
                    Mealy circuits
                    A sequence detector
                    Elimination of redundant states
                    Introduction to VHDL

· The RISC Instruction Set and Assembly Language

                    The MIPS R2000 Assembly Language
                    Instructions' representation in the computer
                    Addressing modes
                    Compiler, linker, loader
                    RISC vs. CISC

· Compiler, linker, loader

· Single Cycle Architecture

Execution phases
                    Building a CPU from basic components
A simple implementation scheme: datapath and control
                    The problems of single cycle.

· Multi Cycle Architecture

Implementation
                    Control unit

· Multi-Cycle Control Unit

Flip-Flops review,

Finite State Machine Design, Moore and Mealy,

PLA

ROM

Microprogramming

Exceptions and Interrupts

· Pipelined Architecture

Pipelined datapath
                    Pipelined control

·          Pipelined Architecture - Hazards detection and resolution

Nops and bubbles
                    Forwarding
                    Branch hazards

·         January 11 and 12: Cache

·        January 18^th: The Pentium(r) II/III Processor - Compiler on a Chip (PDF), DAN DAVID 002

In this lecture we will give a brief overview of the ingredients of modern processor micro-architecture in general and will describe its usage in the Intel Pentium II/III processor family. As time permits, we will discuss the aspects of power and energy in novel processors and will show how it is reflected in the new Intel Pentium M Processor.

Ronny Ronen is a Senior Principal Engineer/Researcher and the director of the Intel's Microprocessor Research Lab in Haifa, Israel, focusing on microarchitecture research. Ronny was heavily involved in the definition stages of the Intel Pentium M processor. He has been with Intel for 22 years. Earlier in Intel he led the compiler and performance simulation activities in the Intel Israel Software department. Ronny received his M.Sc. degree from the Technion, Israel Institute of Technology in 1979.  Modern Intel Only relevant slides in Black & White version and Pentium M

· Intel Prescott chip

Past Exams in word format

The following exams do not necessarily indicate what questions will be in this year exam.

Recall this year in addition or instead of the traditional questions there will be questions on

· Transistors

· VHDL

· Related to the Intel lecture

2004 A 2003 A 2003 B

Dec 18, 1998

Mar 17, 1999 Jun 30, 1999 (note corrections is Questions 1& 2)

Oct 13, 1999 Dec 17, 1999

Note that the material of the course has changed recently, so older exams (before 1998) do not reflect the full material of the course. The exams are in word 97 format

Additional material:

Advanced computer periferals

DSP Introduction

Components: 74xx TTL Family Links Software

CPU: Risc CPU Tech Sheets   History

WWW Computer Architecture Page