Computer Science Department

Computer Structure   0368-2159

Semester I, 2002

 

Classes: Tuesday,Wedensdey 10:00-13:00 @ Dan 01

 

 

Lecturers: Yehuda Afek afek@cs.tau.ac.il,  Anat Bremler-Barr,   natali@cs.tau.ac.il

 

 

 

 

 

Teaching Assistant: Alon sheckler shekler@cs.tau.ac.il, Dror Irony irony@cs.tau.ac.il

 

 

 

 

 


Suggested Books

 

·        ·  For the first part of the course:  V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982

·        ·  For the second part of the course:  Patterson Hennessy  Computer Organization Design, The Hardware/Software Interface. Morgan Kaufmann, 1998     Slides

·       ·  Older course book for the first part of the course:  H. Taub  Digital Circuits and Microprocessors. McGraw-Hill, 1982

 

Course outline

 

·        Introduction:  Algebra of logical variable

   

Logical variables and functions
         The OR, AND, NOT functions
         Binary, Octal and Hexadecimal number systems
         Bases transfer of integers and fractions
         The one's complement and two's complement
         Representation of signed numbers
         Boolean Algebra Theorems
         De'Morgan's Theorem
         The XOR, NAND and NOR functions
         Universal System
 
 

·        Basic Logic Building Blocks (Mux, Decoder)   FlipFlops

 

Binary Representations:   Sum of products and products of sums
              Decoders and Encoders (mux)
              A latch with NAND gates
              The need for latch and synchronization
              Clocked FF
              Truth table and timing diagram for a FF
 

·        FlipFlops (continued)   Registers

 

               Two phase clocking and the Master/Slave RS FF
               The JK FF, D and T flip-flps
               Shift registers
 

·        Registers,   Counters,   Simplification of Logical Functions

 

               Serial to parallel
               Parallel to serial
               Serial implementation of a full adder
               Counters and dividers
               Ripple counter and a synchornious counter
               Non-binary counters
 

·         Karnaugh Maps, Finite state machine (FSM), Sequential Circuits

 

   Simplification of Logical functions using Boolean Algebra Theorems
    Simplification using Karnaugh Maps
    Circuit implementation
    The Don't care utility for function minimization
    Internal, external and input states
 

·         Sequential Circuits

 

              The state and transition diagrams
              Mealy circuits
              A sequence detector
              Elimination of redundant states
              Implementation of an Up-down counter with a FSM
 

·        The RISC Instruction Set and Assembly Language

 

              The MIPS R2000 Assembly Language
              Instructions' representation in the computer
              Addressing modes
              Compiler, linker, loader
              RISC vs. CISC
 

·          Single Cycle Architecture

 

              Execution phasesd

              Building a CPU from basic components good

    A simple implementation scheme: datapath and control
              The problems of single cycle.
 

·        Multi Cycle Architecture

                       

Implementation
              Control unit

·        Pipelined Architecture

    

              Pipelined datapath
             Pipelined control

  

·        Pipelined Architecture:  Hazards detection and resolution

 

   Nops and bubbles
   Forwarding
   Branch hazards
 

·        Cache

 


 

Links to related course material

Lecture Notes of last semester course here

 

 

Past Exams

 

Note that the material of the course has changed recently, so older exams (before 1998) do not reflect the full material of the course. The exams are in word 97 format

Oct 14, 1998    Dec 18, 1998

Mar 17, 1999    Jun 30, 1999  There was a correction is Questions 1 and 2.

Oct 13, 1999    Dec 17, 1999

Feb 09, 2000