tauniceSchool of Computer Science, Tel-Aviv University

Computer Structure  


תשס"ח, סמסטר א'  ,2007-8 (Winter Semester)


Yehuda Afek



Nathan Intrator


Teaching Assistant:

Boris Korenfeld


Administration & Messages

Please remember to fill in the evaluation forms for

Both: Nathan and Yehuda


VHDL will not be part of the test in this semester


TARGILIM (homework) Homework grade calculation: To get the full grade on the homework you have to submit **ALL** the exercises.  The homework grade will be the average of all of them.




Schrieber  006



Schrieber  006

News and Updates

End of Pentium 4                300 TByte Disk          New Core Duo

AMD Quad Core                 AMD Triple Core

Suggested Books

·         Course summary and past tests can be found on the students page

·         For the first part of the course:  V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization. McGraw-Hill, 1982

  • H. Taub  Digital Circuits and Microporcessors.   McGraw-Hill 1982

·         An introductory book about VHDL such as: VHDL Cook Book, Ref Manual  See also VHDL Archive

·         For the second part of the course:  Patterson Hennessy  Computer Organization Design, The Hardware/Software Interface. Morgan Kaufmann, 1998     Slides

·         Older course book for the first part of the course:  H. Taub 

·         Digital Circuits and Microprocessors. McGraw-Hill, 1982


Final Exam 80%

Exercises 20% (5 exercises)

Full set of lectures of Limor (Sem A 2007-8)

Course outline :

             Introduction                          Scribe2                                   Exercice Classes 2006

An introduction to the course

What is it Computer Structure?

The importance of Instruction sets

Memory hierarchies
      Technological forces driving computer structure
      Silicon -> Transistors -> logical gates
      Implementing basic logical circuits from CMOS transistors

     Java applets simulating CMOS transistor implementations of digital logic gates see also second demo


Representation of numbers          Scribe1                       Scribe2  Shirly_Scribe


Binary, Octal and Hexadecimal number systems

Bases transfer of integers and fractions

The one's complement and two's complement

Representation of signed numbers

            Algebra of logical variables               Shirly_Scribe

Logical variables and functions
The OR, AND, NOT functions
Boolean Algebra Theorems
De'Morgan's Theorem
The XOR, NAND and NOR functions
Universal System

            Karnaugh Maps, Combinatorial Circuits     PDF  

Shirly_Scribe             Limor_Scribe                Michal_Scribe

Simplification of Logical functions using Boolean Algebra Theorems
Simplification using Karnaugh Maps
Circuit implementation
The Don't care utility for function minimization

Basic Logic Building Blocks (Mux, Decoder)      PDF


  Decoders and Encoders (mux)

  Introduction to VHDL 

             Flip Flops       Scribe Shirly   Scribe Michal

A latch with NAND gates
The need for latch and synchronization
Clocked FF
Truth table and timing diagram for a FF
Two phase clocking and the Master/Slave RS FF
The JK FF, D and T flip-flops
Shift registers 

             Registers, Counters, Simplification of Logical Functions               

            Scribe Michal                          Shirly_Scribe

Serial to parallel
Parallel to serial
Serial implementation of a full adder
Counters and dividers
Ripple counter and a synchronous counter
Non-binary counters

  Analog to Digital Conversion         VHDL Quick Primer    Scribe Michal   Shirly_Scribe

  VHDL   Introduction to VHDL     Tutorial            Ref Manual

  Sequential Circuits    (FSM)

               The state and transition diagrams
               Mealy circuits
               A sequence detector
               Elimination of redundant states

               Review VHDL

               The RISC Instruction Set and Assembly Language                     


 The MIPS R2000 Assembly Language    

              Mips Instruction Set Architecture (ISA) Spec       

              Instructions' representation in the computer
                        Addressing modes
              Compiler, linker, loader
              RISC vs. CISC


            Single Cycle Architecture                  Scribe Michal                          Shirly_Scribe

              Execution phases
              Building a CPU from basic components
              A simple implementation scheme: data path and control
              The problems of single cycle.

 Pipelined Architecture                      Scribe Michal              Shirly_Scribe

              Pipelined datapath
              Pipelined control
             Pipelined Architecture - Hazards detection and    resolution

 Nops and bubbles
 Branch hazards

 Cache                        Scribe Michal


Branch Prediction

Supplementary material:

            Multi Cycle Architecture    

              Control unit

            Multi-Cycle Control Unit

Flip-Flops review,

Finite State Machine Design, Moore and Mealy,


Microprogramming,  Exceptions and Interrupts

Past Exams

The following exams do not necessarily indicate what questions will be in this year exam. 

In addition or instead of the traditional questions there will be questions on:

·         Transistors

·         A/D

2007-8 Sem A (with Solution)

2005AB  2005A   2005C

2004 A    2003 A  2003 B

Dec 18, 1998

Mar 17, 1999    Jun 30, 1999  (note corrections is Questions 1& 2)

Oct 13, 1999    Dec 17, 1999

Solutions for the Exam from Feb 25:  Full Exam, Quest 2, Quest 1,5



*Note that the material of the course has changed recently, so older exams (before 1998) do not reflect the full material of the course. The exams are in word 97 format.

*(Note that since last year VHDL has been added and is an integral part of the course.


  Additional material:

Advanced computer periferals

DSP Introduction

Components: 74xx TTL Family  Links  Software

CPU: Risc CPU Tech Sheets    History

WWW Computer Architecture Page 


Past guest talks:

The Pentium(r) II/III Processor - Compiler on a Chip (PDF),

In this lecture we will give a brief overview of the ingredients of modern processor micro-architecture in general and will describe its usage in the Intel Pentium II/III processor family.  As time permits, we will discuss the aspects of power and energy in novel processors and will show how it is reflected in the new Intel Pentium M Processor.

Ronny Ronen is a Senior Principal Engineer/Researcher and the director of the Intel's Microprocessor Research Lab in Haifa, Israel, focusing on microarchitecture research.  Ronny was heavily involved in the definition stages of the Intel Pentium M processor.  He has been with Intel for 22 years.  Earlier in Intel he led the compiler and performance simulation activities in the Intel Israel Software department.  Ronny received his M.Sc. degree from the Technion, Israel Institute of Technology in 1979.  Modern Intel     Only relevant slides in Black & White version   and   Pentium M

Intel Prescott chip